1. Technical Field
The present invention relates generally to integrated circuits and, in particular, to synchronizing global clocks in 3D stacks of integrated circuits by shorting the clock network.
2. Description of the Related Art
A three-dimensional (3D) stacked chip includes two or more electronic integrated circuit chips (referred to as strata or stratum) stacked one on top of the other. The strata are connected to each other with inter-strata interconnects that could use C4 or other technology, and the strata could include through-Silicon vias (TSVs) to connect from the front side to the back side of the strata. The strata could be stacked face-to-face or face-to-back where the active electronics can be on any of the “face” or “back” sides of a particular stratum.
However, the synchronization of a global clock for the stacked chip poses a number of problems. These problems relate to a set of constraints that should be imposed on the synchronization. The set of constraints include, but are not limited to, the following: strata must be testable at the target clock frequency before stacking; inter-stratum and within stratum skews must be small, similar to 2D chip; low power and area overheads; robust to all sources of variations including process, voltage, temperature and functional yield; applicable to both grid and non-grid clock network; and compatible with voltage and frequency scaling where the supply voltage and the frequency of the 3D stacked chip is changed during operations to optimize performance.